phase1:phase1:runber
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| phase1:phase1:runber [2016/07/13 09:59] – leac | phase1:phase1:runber [2016/08/23 17:43] (current) – leac | ||
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| * Differntial signal IN: Right two resistors next to CON500C | * Differntial signal IN: Right two resistors next to CON500C | ||
| + | === Settings on Switch S2 === | ||
| + | |||
| + | * 1: Should be always on | ||
| + | * 2: Datatype. OFF: fixed pattern, ON: PRBS | ||
| + | * 3: Errortype. OFF: no automatic error detection, ON: 1 error/s. Use OFF setting | ||
| + | |||
| + | === Buttons === | ||
| + | |||
| + | * SW6: Reset FPGA | ||
| + | * SW7: Reset error counter | ||
| + | * SW5: Set Synch | ||
| + | * SW8: Set Sequence | ||
| + | * SW4: Introduce bit error | ||
| + | |||
| + | * To run with idle pattern: push SW6, SW7 | ||
| + | * To run with random bit stream at 400Mbits: push SW6, SW8, SW7 | ||
| + | * To run with random bit stream at 100Mbits: push SW6, SW5, SW7 | ||
| + | |||
| + | === LEDs === | ||
| + | * DS7: Blinking green if FPGA ready | ||
| + | * DS6: Green light if no error detected, turns off if error detected | ||
phase1/phase1/runber.1468396776.txt.gz · Last modified: 2016/07/13 09:59 by leac
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