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How to run BER test

  • Connect UZH L3 Testboard with LVDS input signal connected
  • Connect a POH with fiber 2 connected to L3 position
  • Connect Dani's BER board:
CON880A: Data OUT: Ethernet cable going to UZH L3 Testboard
CON500C: Data IN:  Ethernet cable coming from FED
  • Turn on CCU and opto power
  • Configure POH. Login to cmspixel2:
cd TriDAS/pixel/BPixelTools/ccu
> reset
> piareset all
> scanccu
> i2c 0x13 0x1a 10
> i2c 0x13 0x1b 0
  • Initialize digital FED 0x4C000000. Login to cmspixel:
cd TriDAS/pixel/BPixelTools/initfed
> initFitelN

Probing Data OUT and Data IN on BER testboard

  • CON 805/806: Differential signal OUT
  • Differntial signal IN: Right two resistors next to CON500C

Settings on Switch S2

  • 1: Should be always on
  • 2: Datatype. OFF: fixed pattern, ON: PRBS
  • 3: Errortype. OFF: no automatic error detection, ON: 1 error/s. Use OFF setting


  • SW6: Reset FPGA
  • SW7: Reset error counter
  • SW5: Set Synch
  • SW8: Set Sequence
  • SW4: Introduce bit error
  • To run with idle pattern: push SW6, SW7
  • To run with random bit stream at 400Mbits: push SW6, SW8, SW7
  • To run with random bit stream at 100Mbits: push SW6, SW5, SW7


  • DS7: Blinking green if FPGA ready
  • DS6: Green light if no error detected, turns off if error detected
phase1/phase1/runber.txt · Last modified: 2016/08/23 17:43 by leac