Differences

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--- phase1:phase1:runber [2016/07/13 09:56] – leac
+++ phase1:phase1:runber [2016/08/23 17:43] (current) – leac
@@ Line 25: / Line 25: @@
   > initFitelN
+=== Probing Data OUT and Data IN on BER testboard ===
-  * Connect UZH L3 Testboard with LVDS input signal connected
-  * Connect a POH with fiber 2 connected to L3 position
-  * Connect Dani's BER board:
-  CON880A: Data OUT: Ethernet cable going to UZH L3 Testboard
+  * CON 805/806: Differential signal OUT
-  CON500C: Data IN:  Ethernet cable coming from FED
+  * Differntial signal IN: Right two resistors next to CON500C
+=== Settings on Switch S2 ===
+  * 1: Should be always on
+  * 2: Datatype. OFF: fixed pattern, ON: PRBS
+  * 3: Errortype. OFF: no automatic error detection, ON: 1 error/s. Use OFF setting
+=== Buttons ===
+  * SW6: Reset FPGA
+  * SW7: Reset error counter
+  * SW5: Set Synch
+  * SW8: Set Sequence
+  * SW4: Introduce bit error
+  * To run with idle pattern: push SW6, SW7
+  * To run with random bit stream at 400Mbits: push SW6, SW8, SW7
+  * To run with random bit stream at 100Mbits: push SW6, SW5, SW7
+=== LEDs ===
+  * DS7: Blinking green if FPGA ready
+  * DS6: Green light if no error detected, turns off if error detected

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