phase1:phase1:runber
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| phase1:phase1:runber [2016/07/13 09:55] – leac | phase1:phase1:runber [2016/08/23 17:43] (current) – leac | ||
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| > initFitelN | > initFitelN | ||
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| - | Connect UZH L3 Testboard with LVDS input signal connected | + | === Probing Data OUT and Data IN on BER testboard |
| - | * Connect a POH with fiber 2 connected to L3 position | + | |
| - | * Connect Dani's BER board: | + | |
| - | * Initialize digital FED 0x4C000000. Login to cmspixel: | + | |
| - | * Use buttons | + | |
| + | * CON 805/806: Differential signal OUT | ||
| + | * Differntial signal IN: Right two resistors next to CON500C | ||
| + | |||
| + | === Settings on Switch S2 === | ||
| + | |||
| + | * 1: Should be always on | ||
| + | * 2: Datatype. OFF: fixed pattern, ON: PRBS | ||
| + | * 3: Errortype. OFF: no automatic error detection, ON: 1 error/s. Use OFF setting | ||
| + | |||
| + | === Buttons === | ||
| + | |||
| + | * SW6: Reset FPGA | ||
| + | * SW7: Reset error counter | ||
| + | * SW5: Set Synch | ||
| + | * SW8: Set Sequence | ||
| + | * SW4: Introduce bit error | ||
| + | |||
| + | * To run with idle pattern: push SW6, SW7 | ||
| + | * To run with random bit stream at 400Mbits: push SW6, SW8, SW7 | ||
| + | * To run with random bit stream at 100Mbits: push SW6, SW5, SW7 | ||
| + | |||
| + | === LEDs === | ||
| + | * DS7: Blinking green if FPGA ready | ||
| + | * DS6: Green light if no error detected, turns off if error detected | ||
phase1/phase1/runber.1468396544.txt.gz · Last modified: 2016/07/13 09:55 by leac
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