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phase1:phase1:runber [2016/07/13 09:56] – leac | phase1:phase1:runber [2016/07/13 10:05] – leac | ||
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- | + | === Probing Data OUT and Data IN on BER testboard === | |
- | * Connect UZH L3 Testboard with LVDS input signal connected | + | |
- | * Connect a POH with fiber 2 connected to L3 position | + | |
- | * Connect Dani' | + | |
- | | + | |
- | | + | |
+ | === Settings on Switch S2 === | ||
+ | |||
+ | * 1: Should be always on | ||
+ | * 2: Datatype. ON: fixed pattern, OFF: PRBS | ||
+ | * 3: Errortype. OFF: no automatic error detection, ON: 1 error/s. Use OFF setting | ||
+ | |||
+ | === Buttons === | ||
+ | |||
+ | * SW6: Reset FPGA | ||
+ | * SW7: Reset error counter | ||
+ | * SW5: Set Synch | ||
+ | * SW8: Set Sequence | ||
+ | * SW4: Introduce bit error | ||
+ | |||
+ | * To run with idle pattern: push SW6, SW7 | ||
+ | * To run with random bit stream at 400Mbits: push SW6, SW8, SW7 | ||
+ | * To run with random bit stream at 100Mbits: push SW6, SW5, SW7 |